Exclusive or circuit using nor logic



Jan. 22, 1963 w. w. BOYLE 3,075,093

EXCLUSIVE 0R CIRCUIT usmc NOR LOGIC Filed Dec. 19. 1960 A N 4| B M 42 0 W N 43 54 54 AB 55 NOR A+B NOR as B Z5 53% NOR A+B 74, 2 NOR B2 CARRY A+B 7H NOR 1 NOR A2 5 C+A B 73\ 8 BE NOR m NOR mva R 'msu M 69 (64 c AVB J NOR NOR 'A+ 7s e3 =83 BORROW N 0R uvmvrom w WILLIAM w. BOYLE 1w AGENT other so that the United States Patent 3,075,093 EXCLUSIVE 0R CIRCUIT USING NOR LOGIC William W. Boyle, La Grangeville, N.Y., assiguor to International Business Machines Corporation, New York, N.Y., a corporation of New York Filed Dec. 19, 1960, Ser. No. 76,641 1 Claim. (Cl. 307-885) This invention relates to apparatus for performing logical operations upon binary signals, and more particularly, to such apparatus composed of interconnected logical circuit elements.

The fundamental logical circuit elements in digital computer apparatus has been the AND, OR, and NOT circuits. Each of these circuits performs a different type of logical operation. In the past it has been necessary to use a combination of these or other logical circuit elements in order to construct digital computing apparatus such as an EX clusive OR circuit, or a Full Adder and Subtractor circuit.

The present invention is directed to digital computing apparatus capable of performing the Exclusive OR operation using only a single type of logical circuit element, called the NOR circuit. More efiicient construction and servicing of the apparatus can be achieved by utilizing only a single circuit element. Where there is a plurality of types of circuit elements, problems arise in attempting to locate the proper type of circuit elements adjacent to each interconnections are minimized. Also in servicing such a computer each of the various types of circuit elements ment parts available.

It is an object of the present invention to provide an improved Exclusive OR circuit using only a single type of logical circuit element.

It is a further object Exclusive OR circuit such circuit elements.

of this invention to provide an containing a minimum number of Still another object is to provide an improved Exclusive OR circuit capable of rapid operation.

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.

In the drawings:

FIG. 1 is a block diagram of a NOR circuit used in the invention.

FIG. 2 illustrates a cuitry suitable for NOR circuit shown in FIG. 1.

FIG. 3 is a block diagram of another NOR circuit capable of use in the invention.

FIG. 4 illustrates a preferred embodiment of the circuitry suitable for performing the logical operation of the NOR circuit shown in FIG. 3.

FIG. 5 is a schematic diagram of an Exclusive OR circuit embodying the invention.

FIG. 6 is a schematic diagram of a Full Adder and Subtractor circuit embodying the invention.

The circuit element shown in FIG. 1, called a NOR circuit, is the only circuit element used to construct the Exclusive OR circuit shown in FIG. 5, and the Full Adder and Subtractor circuit shown in FIG. 6. This Exclusive OR circuit may be used in digital computers when their operation calls for an output signal when only one of two binary input signals is present. The Full Adder and Subtractor circuit of FIG. 6 can be used in any computer where the operation calls for either the addition of two binary digits and a carry from the previous binary digit position, or the subtraction of two binary digits and a borrow from the previous binary digit position. This Full preferred embodiment of the cir- 'Adder and Subtractor circuit is capableof providing a signal representing the sum or difference, and signals repmust be stored in order to have replaceperforming the logical operation of the;

represents the presence digital computing apparatus.

ICC

resenting the carry and borrow functions of three binary input signals.

FIG. 1 illustrates the logical operation of a NOR circuit. Three binary signals A, B, and C are applied to the input terminals, 1, 2, and 3, respectively. An output is present on terminal 4 when A is not present, or B is not present, or C is not present. This statement of the output on terminal 4 is expressed in the language of Boolean algebra in FIG. 1 at the terminal 4. The removal or addition of an input results in the removal or addition of a corresponding term in this Boolean expression.

In FIG. 2 a preferred circuit is shown for carrying out the operation of the NOR circuit shown in FIG. 1. A PNP transistor 10 of the junction type is shown having a collector 11, a base 12, and an emitter 13. The collector 11 is biased by the negative voltage supply on terminal 14 through resistor 15. The base 12 is biased by the positive voltage supply on terminal 16 through resistor 17 so that the transistor is not conducting when no signals are connected to the terminals 1-3. Resistors 21-23 are designed so that a negative signal applied to any one or more of the terminals 1-3 causes the transistor 10 to conduct. When the transistor 10 conducts, the output terminal 4 approaches the voltage level of ground 24 connected to the emitter 13. If all of the signals applied to the terminals 1-3 are positive the transistor 10- does not conduct and the voltage level on the output terminal 4 drops approximately to the level of the negative voltage supply on terminal 14.

Referring to FIG. 2, if the presence of the binary signal A is represented by a positive voltage level on terminal 1, and the output on terminal 4 is considered to be present when the more positive voltage level of the ground 24 is approached, the Boolean expression at the output terminal is a statement of when this more positive level is present as a function of the signals applied to the terminals 1-3. For example, if the binary signal A is absent, a negative signal is present on the terminal 1 causing the transistor 10 to conduct. The voltage on output terminal 4 approaches the more positive level of ground 24 which of an output. Thus, the first term of the Boolean expression at terminal 4 is K, which in Boolean language means an output is present on terminal 4 when the binary signal A is not present on terminal 1. In a like manner, it can be seen that, when the binary signal B is not present there will be an output, or when the binary signal C is not present there will be an output.

The proper value of resistors and potential sources in FIG. 2 can be chosen so that the output on terminal 4 may be connected to one or more of the input terminals 1-3 of another NOR circuit. A series of NOR circuits can be connected together in this manner to construct The NOR circuit of FIG. 1 is called the Stroke function NOR circuit and will be referred to as such.

Shown in FIG. 3 is another NOR circuit capable of implementing the circuits in FIGS. 5 and 6. This NOR circuit performs a slightly different operation and is called the Dagger function NOR circuit. Three binary signals A, B, and C are shown applied to the terminals 31-33 respectively of the Dagger function NOR circuit in FIG. 3. The Boolean expression at the output terminal 34 is an algebraic statement of when this output is present as a function of the three binary signals on terminals 31-33. The output is present on terminal 34 only when the binary signal A is not present and B is not present and C is not present. One or more inputs may be added or removed, resulting in the removal or addition of a corresponding term in the Boolean expression at terminal 34.

The Dagger function NOR circuit shown in FIG. 3 is the dual of the Stroke function. NOR circuit shown in FIG. 1. That is, by applying the complement of the algebra as taught Company, 'inc., 1n the following manner:

This may be illustrated as follows:

Dagger function NOR circuit 3 inputs: K; B; O v 7 output: X-B -6=A-B-C=Z.+B+B

Stroke Function NOR Circuit Output It may also be shown that the stroke function NOR circuit in FIG. 1 is the dual of the Dagger function NOR circuit shown in FIG. 3 as follows:

not conducting, the voltage onterminal 34 approaches the potential of the positive voltage supply on terminal 45. The voltage on terminal 34 is positive only if all of the voltages on terminals 3133 are negative. The Boolean expression at the output terminal 34 inFIGA is an alge-1 braic statement of the presence and absence of the signal on terminal 34. The presence of the biuaryisignals A, B, and C is represented by a positive voltage. The resistors and potential sources in FIG. 4 can be designed so that several stages of NOR circuits can operate with their inputs and outputs coupled together. As in the case of the Stroke function NOR circuit, a series of Dagger function NOR circuits may be connected together to construct digital computing apparatus.

In FIG. 5 all of the NOR circuits'have two inputs and a single output and each performs the logical operation shown in FIG. .1 Binary signals A and B are applied to terminals 58 and .59 respectively. The Boolean expressions at the output of NOR circuits 51-54 arean algebraic s5 istatementof the presence and absence of these outputs Where the circuit shown in FIG. 6 isto perform the at a function of the presence and absence of the binary. Full Subtractoroperationonly, NOR circuit 74 is not reinput signals Aand B. The interconnections are carefully q ired- Here the binary Signals A and B represent the select ed'so that a minimum number of NOR circuits are digits to be subtracted; B is subtracted from A. The used to term the Exclusive OR function at terminal '55. 7a a y signal C represents t r w function from the The Boolean expressions at theoutput of NOR circuits 52-54 may be derived using the basic principles of Boolean in the text Arithmetic Operations In Digital Computers by R. K. Richards, D.'Van Nostrand 45 that the complement of 50 Sum NOR circuit 73 NOR circuit 52 inputs: A; K-l-B output: K++=K+AB=K+B NOR circuit 53 inputs: K-l-B; B output: K+I+B=A-B+B=A+B NOR circuit 54 inputs: K-l-B; A-l-B output: K+B+A+B=A-B+K-B=A B The Exclusive OR circuit in FIG. 5 is included in the circuit of FIG. 6 by NOR circuits 61-64 along with their Stroke f n tion NOR circuit FIG 1 15 interconnections. Additional NOR circuits 71-75 are inputs: s5; 6 added to complete the Full Adder and 'Subtractor opera wtlOIl. Output! -l- -l- +B+. Referring to FIG. 6, where the circuit is to perform the Dagger function NOR circuit output Full Adder operation only, NOR circuit 75 is not required. As will be described later in more detail this duality of The binary slgilals A and B lepresentmg the dlglts l be the Stroke and Dagger function enables the circuits of apPhed to the'termtnals 6s and 69 Q FIG. 5' and FIG. 6 to be implemented in either one of The binary signal f .Carry .functmn from these NOR circuits. the next lower binary digitposltion 1S appliedto the ter- In FIG. 4, a preferred circuit is shown capable of per- I The N .clrcults 6x764 qperate m the.1demi' forming the operation of the Dagger function NOR cir f manner described m with the Exfluswe R cuit shown in FIG. 3. The NPN transistor 403s of the F Q- The d P the C 818ml C to junction type and has a collector 41,"a base 42, and an N clrcmt u e the q a term the Boolean emitter 43. A positive voltage supply on terminal 45 expression at l PU of NOR circuit 6 Each the supplies the bias to collector 41 through resistor 46. The oIltPmS fmm N circuits 1' am utilized y t a base 42 is biased by the negativc potential on terminal 47 tioflal NOR r u 71-75 in Order t0 g n rate the Sum through the resistor 48, so that when no signals are conand Carry functions. The Boolean expression at the outnected to the terminals 31-33, the transistor is not conput of .NOR circuits 71 and 72 may be derived as follows: ducting. The resistors 51-53 are designed so that, when a Y positive signal is applied to anyone or more of the ter- OR cir ui 71 minals 31-33, the transistor is caused to conduct. inputs: C; 'O-l-A tT-B When the transistor 40 is conducting, the voltage on ter- 17-?" minal 34 approaches the voltage level of the ground 54 l i C' ;'B p+ 'A connected to the emitter 43. When the transistor 40 is NOR i it 72 40 ut 1 +B; +.AB; .Arl

The inputs of the Sum NOR circuit 73 are chosen so 7 e the Sum function for the three binarysignals A, B, and C, is generated on terminal 81. The Boolean expression for the output of Sum NOR circuit 73 may be derived as follows:

inputs: E+AB C+AB output: C+AB+C+AB; (outlets-.112. c+A:,zB I c-AB+6-AB=sUM 1 The inputs to Carry NOR circuit 74 are chosen so that the Carry function of the three binary signal inputs is generated onterminal 82. The Boolean expression for the Carry NOR circuit '74 maybe derived as follows:

Carry NOR .circuit 74 inputs: Kai- B; (I l-AXLE next lower binary digitposition.

function and the Difference The output from the Sum NOR circuit 73 now represents the Difference function for the three binary'signals; No change in conne ctions is needed since the Boolean expression for the Sum i function is the same. The

' 5 inputs to the Borrow NOR circuit 75 are chosen so that the output on terminal 83 represents the Borrow function for the three binary signal inputs. The Boolean expression for the output of the Borrow NOR circuit 75 may be derived as follows:

circuit 75 can remain in the circuit of FIG. 6 without interfering with operation of the other. Another advantageous feature of this Full Adder and Subtractor circuit 15 is that the Carry or Borrow input signal on terminal 70 propagates through only two stages of NOR circuits before arriving at the output of the Carry NOR circuit 74 or Borrow NOR circuit 75. This allows a more rapid opera tion of the computer apparatus and is especially advantageous Where a number of such Full Adder and Subtractor circuits are operated in parallel, one for each binary digit position. In this case, the Carry or Borrow signal must propagate through a plurality of such circuits as shown in FIG. 6. The number of stages of NOR circuits that this signal must propagate through within each Full Adder and Subtractor directly affects the total time of propagation through the entire array of binary digit positions. 1

The Exclusive OR circuit shown in FIG. 5 can be implemented by using the Dagger function NOR circuit in FIG. 3. For this implementation, the complement of the binary signals A and B are applied to the terminals 58 and 59 and the complement of the Exclusive OR function is generated at terminal 55. This may be shown by deriving the Boolean expressions for the outputs of each NOR circuits 51-54 as follows:

NOR circuit 51 inputs B output: A-Ts-K-B=A-1+K-B=AB The Full Adder and Subtractor circuit of FIG. 6 can be implemented using the Dagger function NOR circuit of FIG. 3 by applying the complement of the signals A, B,

and C to the terminals 68-70. The complement of the functions shown at the terminals 8183 is generated. The

Boolean expressions for the outputs of NOR circuits 64 2,901,637

and 71-75 may be derived as follows: NOR circuit 64 6 NOR circuit 72 20 Borrow NOR circuit 75 Since the complement of the binary signals are as readily available as the true form of the binary signals in most digital computers, the Dagger function implementation is 30 as useful as the Stroke function implementation. Whether the Stroke function NOR circuit or the Dagger function NOR circuit is employed, the circuits as shown in FIGS. 5 and 6 operate successfully without any changes in interconnections.

While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.

What is claimed is:

An Exclusive OR circuit capable of accepting two binary signals comprising: a first, a second, a third, and a fourth NOR circuit; and circuit means connecting said I binary signals to said first NOR circuit, one of said binary signals to said second NOR circuit, and the other of said binary signals to said third NOR circuit, the output of said first NOR circuit to said second and third NOR circuits, and the output of said second and third NOR circuits to (it) said fourth NOR circuit, whereby the output of said fourth NOR circuit represents the Exclusive OR function of said two binary signals.

References Cited in the file of this patent UNITED STATES PATENTS 2,815,913 Lucas Dec. 10, 1957 2,868,999 Garfinkel et a1 Jan. 13, 1959 2,894,687 Raymond et al July 14, 1959 Wang Aug. 25, 1959 OTHER REFERENCES Kellet: The Elliott Sheifer Stroke Static Switching Systern, Electronic Engineering (September 1960).

(Page 537-Figure 15 relied on.) 

